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Si4840/44-A10
Table 4. 2-Wire Control Interface Characteristics 1,2,3
(V DD = 2.7 to 3.6 V, T A = –15 to 85 °C)
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO ? Setup
(START)
SCLK Input to SDIO ? Hold
(START)
SDIO Input to SCLK ? Setup
SDIO Input to SCLK ? Hold 4,5
SCLK input to SDIO ? Setup
(STOP)
STOP to START Time
SDIO Output Fall Time
Symbol
f SCLK
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t BUF
t f:OUT
Test Condition
Min
0
1.3
0.6
0.6
0.6
100
0
0.6
1.3
Typ
—
—
—
—
—
—
—
—
—
—
Max
400
—
—
—
—
—
900
—
—
250
Unit
kHz
μs
μs
μs
μs
ns
ns
μs
μs
ns
C b
20 + 0.1 -----------
1pF
C b
20 + 0.1 -----------
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
t f:IN
t r:IN
C b
t SP
—
—
1pF
—
—
—
300
50
50
ns
pF
ns
Notes:
1. When V D = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si484x delays SDIO by a minimum of 300 ns from the V IH threshold of SCLK to comply with the minimum t HD:DAT
specification.
5. The maximum t HD:DAT has only to be met when f SCLK = 400 kHz. At frequencies below 400 kHz, t HD:DAT may be
violated as long as all other timing parameters are met.
6
Rev.1.0
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